Systems on chip (SoC) and processor design teams are challenged to meet aggressive power, performance and area requirements. As chip complexity grows, teams must verify thousands of lines of code to ...

In this paper, we examine the need for formal sequential equivalence checking across pairs of RTL models. We present scenarios that call for modifying the sequential behavior of RTL models while ...

A class of sequential designs for estimating the percentiles of a quantal response curve is proposed. Its updating rule is based on an efficient summary of all of the data available via a parametric ...

Different design approaches, techniques, and architectures are widely used for synchronous sequential machines. In particular, the micro-programmed machine approach offers important features such as ...