TechRepublic

Low Power State Retention Technique for CMOS VLSI Design

Mobile computing and mobile communication applications which are powered by battery, the battery life is a major concern. Leakage power dissipation is critical in VLSI circuits as the battery leaks ...
NextBigFuture

DARPA Semiconductor Starnet beyond CMOS research targets ten thousands times power improvement

The DARPA Semiconductor Technology Advanced Research Network (STARNet) program is a government-industry partnership combining the expertise and resources from select defense, semiconductor, and ...
EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
Design-Reuse

VLSI Design: Future of Wireless Communication

As a technology enthusiast, I have always been fascinated by the rapid advancements in the field of wireless communication. The ability to connect with people and devices wirelessly has revolutionized ...
Electronics Weekly

VLSI Symposium: Imec’s low-power UWB transceiver ranges to 1.4mm

Belgian lab Imec is claiming record ranging precision and power consumption for a novel 6 – 9GHz IEEE 802.15.4z UWB (ultra-wide-band) impulse-radio transceiver: 1.4mm ranging, and 8.7mW Tx plus 21mW ...
TechRepublic

Low Power VLSI CMOS Design by DCG Technique

The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown ...