Business Wire

ASSET’s Board Bring-Up Solution First to Validate, Test and Debug Designs Using the Intel Microarchitecture Codenamed Haswell

RICHARDSON, Texas--(BUSINESS WIRE)--With new tools for the ASSET® ScanWorks® platform for embedded instruments, design engineers can for the first time structurally verify, functionally test, analyze ...
EDN

AppliedMicro, ASSET collaborate on SourcePoint debugger to accelerate development of cloud applications based on X-Gene Server on a Chip solution

Richardson, TX, and Sunnyvale, CA (February 25, 2014) – ASSET® InterTech and Applied Micro Circuits Corporation (NASDAQ: AMCC), also known as AppliedMicro®, have collaborated on enabling ASSET's ...
Business Wire

ASSET’s New FPGA-Controlled Test (FCT) Inserts and Operates a Board-Tester-in-a-Chip

RICHARDSON, Texas--(BUSINESS WIRE)--With new tools for the ASSET® ScanWorks® platform for embedded instruments engineers can simply select instruments they need, set their parameters and insert them ...
Electronic Design

Learn ABCs Of JTAG Boundary-Scan Testing With Software Bundle

Boundry-scan testing (IEEE1149.1/JTAG) is a novel procedure for some test engineers and technicians. But ScanWorks Interconnect Development Station version 3.4 from Asset Intertech should ease their ...
EDN

How to test high-speed memory with non-intrusive embedded instruments explained in white paper – Challenges an

How to test high-speed memory with non-intrusive embedded instruments explained in white paper – Challenges and tradeoffs of testing DDR3, DDR4 and other buses described in technical paper Richardson, ...
Electronic Design

ASSET Joins PCI-SIG

ASSET ® InterTech, a supplier of tools for embedded instrumentation, has joined the PCI-SIG ® and plans to participate in the group’s upcoming interoperability workshops. As a result, manufacturers of ...